International Research Journal of Innovations in Engineering and Technology - IRJIET International Open Access, Monthly, Peer Reviewed, Reputed Journal ISSN (online): 2581-3048

Impact Factor (2025): 6.9

DOI Prefix: 10.47001/IRJIET

Low Power Design of Highly Secured Crypto Processors

Abstract

In this paper we propose the design of ring learning with errors (LWE) crypto processors using Number Theoretic Transform (NTT) cores and Gaussian samplers based on the inverse transform method. The NTT cores are designed using radix-2 and radix-8 decimation-in-frequency NTT algorithms and pipeline architectures. The designed Gaussian samplers are an optimized parallel implementation of the inverse transform method and they use pipeline architecture to generate a sample every clock cycle after the latency period, that is, the output is Obtained in a fixed time achieving timing attack resistant ring–LWE crypto processors. Also, taking into account the national institute of standards and technology recommendation, a random number generator is designed to generate the input of the Gaussian sampler.

Country : India

1 Rajan Lavanya2 M.Vidhyia3 G.Kanagaraj

  1. M.E Scholar, Department of VLSI, AVS Engineering College, Salem, Tamilnadu, India
  2. Assistant Professor, Department of ECE, AVS Engineering College, Salem, Tamilnadu, India
  3. Assistant Professor, Department of ECE, AVS Engineering College, Salem, Tamilnadu, India

IRJIET, Volume 2, Issue 1, March 2018 pp. 32-37

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