Design of 16bit 6t SRAM Using Different CMOS Technologies Using Cadence Virtuoso Tool
Abstract
Static Random Access
Memory (SRAM) has been an important memory device in VLSI circuits. SRAM is
used widely because of its huge storage capacity and can be accessed in less
time with low power consumption. This paper presents design and implementation
of 16Bit 6T SRAM using different CMOS technologies using Cadence Virtuoso tool.
Due to the requirement of more storage, usage of 16-bit SRAM is convenient. The
performance analysis of SRAM with respect to Power Dissipation and Average
Delay is observed and compared.
Country : India
1 Rodda Srinivas
Assistant Professor, Department of Electronics and Communication Engineering, Malla Reddy College of Engineering for Women, Hyderabad -500100, Telangana, India
IRJIET, Volume 2, Issue 7, September 2018 pp. 16-19
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